HP Press Release - HP Continues Leadership With New, Highest-Performance PA-RISC Microprocessor Original Document

HP Continues Leadership With New, Highest-Performance PA-RISC Microprocessor

Most Powerful PA-RISC Chip Breaks the 1MB On-chip Memory Barrier; Dramatically Reduces Microprocessor Complexity and Overall Computer-system Costs

San Francisco, California. March 12, 1997

Aggressively advancing its leadership in commercial and technical computing and providing customers with a clear roadmap into the future, Hewlett-Packard Company today announced the PA-8500, the company's most powerful microprocessor to date and the industry's first chip to break the 1 megabyte (MB) on-chip memory barrier.

Initial details of the newest member of the PA-8000 family of 64-bit PA-RISC(1) microprocessors were announced here at the Uniforum trade show.

The company's memory breakthrough -- incorporating 1.5MB cache memory on the chip -- gives the PA-8500 five times more on-chip memory than any other microprocessor. The unrivaled cache, enabled by the company's adoption of an advanced .25-micron chip-making process, is expected to deliver breakthrough performance in technical and commercial environments. These applications include Internet access, database access and management, computer-aided design and manufacturing (CAD/CAM), communications and transaction processing.

In fact, the numerous advancements incorporated in the PA-8500 enable it to nearly triple the performance of the company's record-setting PA-8000, which is at the heart of currently shipping HP servers and systems. Additionally, for many applications, such as financial transactions, online airline reservations and routine telephone connections, HP believes the PA-8500 will process information up to five times faster than competitive microprocessors currently on the market.

Performance Breakthrough

HP's adoption of the 0.25-micron process is what gave the company the increased room on the chip; literally every functional component on the device was shrunk into considerably smaller space. HP took the opportunity afforded by this newfound room to incorporate the large on-chip cache memory. The increased space also allowed for a dramatic increase in the amount of intelligence that could be integrated onto the device, greatly improving branch-prediction accuracy.

The 1.5MB of on-chip cache allows the CPU to operate more efficiently while executing instructions. This is particularly advantageous in large commercial applications, such as transaction processing, which routinely require critical applications to be performed simultaneously. Additionally, because systems built around the PA-8500 no longer require expensive cache memory and require fewer parts, the chip cache reduces the overall cost of systems built around the PA-8500.

"The demands of our customers are not standing still, and neither are we," said Richard W. (Rich) Sevcik, HP vice president and general manager of the Systems Technology Group. "They're telling us they want their computers and applications to help them be more competitive, today and into the next decade. We've designed a chip that -- within 18 months -- will drive new computers that will set new applications performance standards. By moving with us through the PA-8000 evolution and our transition to Merced, customers are assured of the industry's strongest road into the future. And nothing could provide more opportunities for competitive advantage."

Innovative Design

Like the PA-8000 and the PA-8200, the PA-8500 is a scaleable 64-bit microprocessor with multiprocessing capabilities, branch prediction and four-way out-of-order execution features, all of which enable industry-leading application performance. The new chip is the company's first to use a .25-micron process and more than 120 million transistors.

By further exploiting the powerful PA-8000 architecture, HP is ensuring that advancements in the PA-8500 also support applications from the PA-8200 and PA-8000. This assures software developers and customers that the investments they have made in applications that run on HP's earlier PA-RISC processors will continue to pay off in the future.

PA-RISC Background

From its inception in 1986, PA-RISC technology was designed to extend well into the next century. HP designed PA-RISC in a simplified, modular fashion to accommodate future technologies, decrease system-design costs and reduce time to market for new products. HP offers the industry's broadest line of RISC-based workstations and business systems and servers and last week was named the leading vendor -- for the seventh consecutive year -- in the commercial RISC/UNIX system market by market-research firm Aberdeen Group of Boston. Aberdeen's research showcased HP as owning 52 percent of the commercial RISC/UNIX system market.

Demand for RISC-based computers has grown steadily since the first commercially available RISC systems were shipped in the mid-1980s. Currently, PA-RISC technology spans HP systems, ranging from low-end workstations to large-scale, 14-way symmetric multiprocessing systems with mainframe-class performance to enterprise parallel servers, scaleable to 224 processors. This demonstrates PA-RISC's inherent scaleability, a primary objective of its original definition, and protects customers' hardware and software investments in this architecture.

Hewlett-Packard Company is the leading global manufacturer of computing, communications and measurement products and services recognized for excellence in quality and support. HP has 112,800 employees and had revenue of $38.4 billion in its 1996 fiscal year.

Information about HP and its products can be found on the World Wide Web at http://www.hp.com.

(1) PA-RISC stands for Precision Architecture-reduced-instruction-set computing.