New IBM POWER3 chip

Performs like eight chips in one

Somers, N.Y., Oct. 5, 1998 . . . IBM today introduced a new, more powerful microprocessor, the POWER3, that performs like eight chips in one.

The chip, which performs up to two billion operations per second, is the next generation of the technology that powered the Deep Blue supercomputer to its historic victory over chess grand master Garry Kasparov last year.

The processor debuted today on IBM's new, high-performance RS/6000 43P Model 260 graphics workstation.

The 64-bit POWER3 microprocessor is a RISC-based (Reduced Instruction-Set Computing) chip developed for IBM's UNIX workstations and servers. The POWER3 is built specifically for the demanding graphic, analysis and simulation programs used by aerospace, automobile and drug manufacturers.

Unlike a typical PC microprocessor, the chip features eight execution units fed by a 6.4 gigabyte-per-second memory subsystem, allowing the POWER3 to outperform competitors' processors running at two to three times the clock speed.

Higher bandwidth and more instructions per cycle are key performance factors for compute-intensive applications, like computer-aided engineering, data mining and online transaction processing.

Another key innovation improves "real-world" application performance by using a technique called hardware memory pre-fetch. This features utilizes an intelligent memory subsystem that recognizes a user's commands and retrieves often-used data. That data is then stored in the chip's cache and is available for quick recall when needed.

The IBM microprocessor roadmap includes enhancements based on the CMOS 7S process, that adopts copper wiring, dramatically boosting performance (planned for 1999), and silicon on insulator technology (in 2000), driving IBM chips into the gigahertz range and beyond by 2001. The RS/6000 technology roadmap provides IBM's workstation customers with the latest advances to solve their most demanding design and simulation challenges.

POWER3 design details

The POWER3 processor core includes two high-bandwidth buses: a 16-byte 6XX architecture bus to main memory and a dedicated 32-byte bus to the L2 cache that runs at processor speed. POWER3 also has an advanced on-chip 64KB data cache and a 32KB instruction cache. It features .25 micron hybrid lithography, five metal layers, and 1088 pin ceramic packaging.

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